1. Field of the Invention
The present invention relates to a method of forming a fine pattern on a substrate in the manufacturing of a semiconductor device or the like. More specifically, the present invention relates to a method of forming a hard mask used to mask a substrate during an etching process in the manufacturing of a semiconductor device or the like.
2. Description of the Related Art
Fabricating a highly integrated semiconductor device entails forming fine patterns on several layers on a substrate. For example, contact holes are formed in a fine pattern in an interlayer insulating layer on the substrate. Contacts are formed in the contact holes to electrically connect circuit features that are formed on opposite sides of the insulating layer. Thus, the basic features, e.g., the contact holes, of a semiconductor device pattern must be formed close together within a small area if the device is to be highly integrated. Accordingly, manufacturing techniques are constantly being developed/improved with an aim to reduce the pitch of the pattern, which is the sum of the width of a basic feature of the pattern and the width of the gap that exists between that feature and the adjacent feature.
Photolithography is one of the techniques used to manufacture highly integrated semiconductor devices, i.e., devices having small design rules. Basically, photolithography is an optical technique by which an image of a desired pattern can be transcribed onto a substrate. Currently, the fineness of the pitch of the pattern that can be transcribed onto the substrate using photolithography has reached a limit due to the limited resolution which can be achieved using photolithography. In particular, the pitch of contact holes which can be formed in an insulating film using photolithography has reached a limit.
However, double patterning has been suggested as a means of overcoming the limitations imposed by the resolution of the photolithography process itself. In a typical double patterning method, first, a mask of repeated features is formed using photolithography. These features are spaced at a predetermined pitch that is relatively large due the limited resolution of the photolithography process. Next, spacers are formed on opposite sides of each of the features of the mask, respectively. Finally, the layer(s) underlying the mask is/are etched using the spacers and the mask together as a hard mask. However, the process by which the spacers are formed tends to form the spacers unevenly on the sides of each feature of the mask pattern. Accordingly, the spacers are often made thicker than desired to ensure that the spacers on the sides of each feature of the mask have the same thickness. Therefore, it is difficult to remove the spacers after using them as a hard mask. Also, the spacers surround each feature of the mask. Therefore, the spacers must be trimmed from the ends of the features of the mask in the case in which line patterns are to be formed using the spacers.
Furthermore, when a double patterning method is used to form contact holes, the dimensions of the contact holes and the layout of the contact holes must be indirectly designed for. That is, the dimensions of the patterns used to form the contact holes are designed with an aim of producing a desired layout of the contact holes. Accordingly, the dimensional accuracy of a fine pattern of contact holes of a semiconductor device depends on the accuracy of the patterns of the hard mask formed during the double patterning method. As is clear from the description above, the hard mask forms an opening around a region of the underlying layer in which a contact hole is to be formed. Therefore, a dimensional error in the hard mask can cause the dimensions of the contact holes to be off by an amount twice the dimensional error of the hard mask in some cases.
Thus, the forming of a fine pattern, and especially of a fine pattern of contact holes, allows for only small margins of error in the critical dimensions (CD) and uniformity of the CD of the pattern of the hard mask. However, the uniformity of the CD of the pattern of a hard mask formed using the conventional double patterning method can not be limited to the degree necessary to fabricate highly integrated semiconductor devices having fine patterns with a design rule of 30 nm or less. That is, the conventional double patterning method produces large numbers of defective products, and is therefore an impediment to the overall productivity of a process of manufacturing highly integrated semiconductor device.